Magnetoresistive memory device and manufacturing method of the same

ABSTRACT

According to one embodiment, there is provided a magnetoresistive memory device. The memory device includes active areas arranged on a semiconductor substrate, resistance change elements arrayed to matrix in an X direction and a Y direction above the substrate, and selective transistors provided to correspond to the respective resistance change elements. A plurality of gate electrodes of the selective transistors are spaced apart at regular intervals in the X direction and arranged along the Y direction. Each of the active areas is provided to cross two of the gate electrodes adjacent to each other, such as to be along the X direction at a portion crossing the gate electrodes, and formed to be inclined with respect to the X direction between the adjacent gate electrodes.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.62/046,039, filed Sep. 4, 2014, the entire contents of which areincorporated herein by reference.

FIELD

Embodiments described herein relate generally to a magnetoresistivememory device and a manufacturing method of the same.

BACKGROUND

A simplest example of MRAM that is a typical resistance change typememory has a structure called 1T/1R. The greatest problem in this memorystructure is how a large amount of current is flowed from a transistorto a resistance change element in a determined cell area.

If a cell transistor size is miniaturized in accordance with a finerarea of the cell, various difficulties should occur. One of thedifficulties is that a device performance is deteriorated (i.e., anoff-leakage current is increased) due to a short channel effect based ona shorter gate length. Another difficulty is that if a cell area is tobe reduced, contact regions for source and drain electrodes also becomesmaller. Therefore, the increase in a parasitic resistance (contactresistance) at this part gives a serious influence to deterioration of acurrent drive.

In future, suppression of the short channel effect and enhancement ofperformance of the current drive need to be attempted by forming socalled a multi-gate device. In this case, a device layout in which atransistor can be easily arranged should be required.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing a planar layout of an MRAM cell according to areferential example.

FIGS. 2A and 2B are views showing a cross-section seen along arrowdirection 4-4′ and a cross-section seen along arrow direction 5-5′ inFIG. 1, respectively.

FIG. 3 is a view showing an active area layout which is electricallyequivalent to the layout shown in FIG. 1, for setting a direction of theactive area to be perpendicular to a word line direction.

FIG. 4 is a view showing a planar layout of an MRAM cell according to afirst embodiment.

FIGS. 5A to 5C are views showing a cross-section seen along arrowdirection I-I′, a cross-section seen along arrow direction II-II′ and across-section seen along arrow direction III-III′ in FIG. 4,respectively.

FIGS. 6A to 6J are plan views showing steps of manufacturing the MRAMaccording to the first embodiment, respectively.

FIGS. 7A to 7J are plan views showing steps of manufacturing the MRAMaccording to the first embodiment, respectively.

FIG. 8 shows an illustration for describing a concept of an MRAMaccording to a second embodiment.

FIG. 9 is a view showing a planar layout of the MRAM according to thesecond embodiment.

FIGS. 10A to 10H are plan views showing steps of manufacturing the MRAMaccording to the second embodiment, respectively.

FIGS. 11A, 11B, and 11C are cross-sectional views seen alongone-dot-chained lines shown in FIGS. 10E, 10G, and 10H, respectively.

DETAILED DESCRIPTION

In general, according to one embodiment, there is provided amagnetoresistive memory device. The memory device comprises active areasarranged and spaced apart at regular intervals, on a semiconductorsubstrate, resistance change elements arrayed in a matrix, in an Xdirection and a Y direction perpendicular to the X direction, above thesubstrate, and selective transistors provided to correspond to therespective resistance change elements, in the active areas. A pluralityof gate electrodes of the selective transistors are spaced apart atregular intervals in the X direction and arranged along the Y direction.Each of the active areas is provided to cross two of the gate electrodesadjacent to each other, such as to be along the X direction at a portionof each of the active areas crossing the gate electrodes, and formed tobe inclined with respect to the X direction between the adjacent gateelectrodes.

Embodiments will be hereinafter described with reference to theaccompanying drawings.

As described above, a device structure in which a parasitic resistanceat a selective transistor portion is small enough to flow a sufficientbidirectional current and the property variation is small needs to beimplemented in a resistance change memory such as an MRAM.

(Referential Example)

First, an example of a cell layout of an MRAM using a resistance changeelement, based on a 6F²-type cell layout proposed for DRAM is described(JP-A 2012-235063 (KOUKAI)).

FIG. 1 is a view showing a planar layout of the MRAM cell according tothe referential example. FIG. 2A is a cross-sectional view seen alongarrow direction 4-4′ in FIG. 1. FIG. 2B is a cross-sectional view seenalong arrow direction 5-5′ in FIG. 1. In the drawings, SUB presents asilicon substrate, AA presents an active area, GC (WL) presents a gateelectrode (word line), M1 presents a source line, M2 presents a bitline, and MTJ presents a magnetoresistive effect element which is one ofresistance change elements. Furthermore, CB presents a source contact,UE presents a contact for MTJ, CT presents a cell transistor, S presentsa source, D presents a drain, VO presents a drain contact, STI presentsa device isolation insulating film, and MC presents a unit cell. Themost characteristic feature of the referential example is that a siliconregion forming AA extends in not vertically or horizontally, butobliquely with a certain angle. This is because where F presents afeature size, a region of 3F forms a cell in a direction vertical withWL long side (i.e., a landscape orientation) and a region of 2F forms acell in a direction parallel with the WL long side (i.e., a portraitorientation). The AA is inclined at about 18 degrees. The reason is thatthe contact region needs to be shared with a transistor of an adjacentcell on the source side and needs to be connected to another M2 via theresistance change element on the drain side. Furthermore, the layout ofobliquely arranging the AA is proposed since the M1 on the source sideand the M2 on the drain side need to be arranged alternately.Accordingly, when a transistor is noticed, the WL serving as the gateelectrode is considered to obliquely overlap the AA.

Such a structure is rarely considered as a problem in a conventionalplanar single gate MOSFET, but has a problem in a double-gate devicerepresented by Fin-FET or a multi-gate device represented by a tri-gate,etc.

If a gate electrode, having a physical gate length, is arrangedobliquely to the fin, in the Fin-FET, a region where a front gate and aback gate of the Fin-FET do not overlap is generated. At such portion,control of an electrostatic potential in the channel should becomesweak, because of no double-gate operation in such region. For thisreason, a leakage current should be great in such case. In addition, inrest of channel region where the front gate and the back gate overlapeach other and the double-gate operation is executed, an effectivechannel length should be short. For this reason, suppression of theshort channel effect of the transistor becomes weak, with the samephysical gate length.

Accordingly, as in the layout shown in FIG. 2, the channel region andthe WL region (gate region) of the transistor need to be definitelyperpendicular to each other, and the front gate and the back gate needto overlap to maximum extent. Furthermore, a wafer notch on a generalstandard wafer is formed in a direction [110]. For this reason, a sidesurface of the active area inclined at an angle of 18 degrees is not asurface (110) or, naturally, is not a surface (100). Accordingly, aninterface state density Dit in the channel region is expected to becomelarge, if the double-gate device uses the side surface of the activearea in the original layout in FIG. 1. This matter is not so desirablefrom the viewpoint of device reliability.

FIG. 3 describes a basic idea on how the same layout as that shown inFIG. 1 can be obtained, under precondition that the direction of theactive area in the channel region is at least set to be vertical withthe direction of the WL long side. All patterns are formed in straightlines of the landscape and portrait orientations in the drawingincluding the contact pad region where the contact region is formed.

A desired layout is implemented by displacing an active area CAA of thechannel portion and an active area PAA of the contact pad portion. Inother words, the CAA is vertical with the gate electrode GC forming theword line WL. In this case, a physical layout can be formed. In fact,however, since a distance (width) in the device isolation region betweencontact pads is short, various manufacturing processes such aslithography, etching, filling of the insulating film in the deviceisolation region can be easily expected to be difficult.

Such difficulties are solved in the embodiments described below.

(First Embodiment)

FIG. 4 is a plan view showing a layout of MRAM cell according to a firstembodiment. FIG. 5A is a cross-sectional view seen along arrow directionI-I′ in FIG. 4, FIG. 5B is a cross-sectional view seen along arrowdirection II-II′ in FIG. 4, and FIG. 5C is a cross-section seen alongarrow direction in FIG. 4, respectively.

Active areas 20 are arranged and spaced apart from each other at regularintervals, on a silicon substrate 10. A plurality of gate electrodes(word lines) 31 are arranged along a Y direction and spaced apart fromeach other at regular intervals in an X direction so as to cross theactive areas 20. Each of the active areas 20 is provided to cross twoadjacent gate electrodes 31. In addition, each of the active areas 20 isprovided in a fin shape along the X direction, at a portion (fin-shapedactive area) 21 crossing each gate electrode 31, and is formed to beinclined from the X direction, at a portion (contact) 22 providedbetween adjacent gate electrodes.

One of parts of the contact portion 22 is a source-side contact region22 a, and the other part is a drain-side contact region 22 b. Thesource-side contact region 22 a and the drain-side contact region 22 bare shaped in a parallelogram as seen from a substrate surface in thevertical direction. An angle θ made between a direction linking a centerof the source-side contact region 22 a and a center of the drain-sidecontact region 22 b, and a channel length direction, is an angle(approximately 18 degrees) presented by θ=tan⁻¹(⅓). This means that acell region is displaced by 6F in the X direction and by 2F in the Ydirection.

A selective transistor 24 for switching comprising the word line 31crossing the fin-shaped active area 21 is formed in each active area 20.Sources of two adjacent transistors 24 are shared in the source-sidecontact region 22 a. The source-side contact region 22 a is connected toeach of source lines 32 arranged along the X direction and spaced apartfrom each other at regular intervals in the Y direction, via a contactplug 25.

MTJ elements 40 are arrayed above the substrate 10, in a matrix in the Xdirection and the Y direction perpendicular to the X direction. A lowerend of each MTJ element 40 is connected to the drain-side contact region22 b via the contact plug 26. An upper end of each MTJ element 40 isconnected to each of bit lines 33 arranged along the X direction andspaced apart from each other at regular intervals in the Y direction,similarly to the source line 32, via a contact plug 27. The bit line 33is formed above the source line 32.

In FIG. 4, a portion 41 surrounded by a broken line indicates a sourcecontact portion, and a portion 42 surrounded by a solid line indicates adrain contact portion.

In the present embodiment, a contact pad region (source-side contactregion 22 a and drain-side contact region 22 b) where the contact isformed is shaped in a parallelogram, which is substantially the same asthat shown in FIG. 1. Furthermore, the active area (fin-shaped activearea) 21 in the channel region is arranged to be vertical with the WLlong side direction. These are the features of the present embodiment.

In the layout of the contact pad region (source-side contact region 22a) shaped in a parallelogram, on the source side, the right channelregion is formed near an upper side of the parallelogram and the leftchannel region is formed near a lower side of the parallelogram. In thelayout of the contact pad region (drain-side contact region 22 b) shapedin a parallelogram, on the drain side, the left channel region is formednear a lower side of the parallelogram and the right channel region isformed near an upper side of the parallelogram. Thus, the same advantageas that in the case of FIG. 1 where the active area is arrangedobliquely can be obtained. Furthermore, since the gate electrode and thechannel region are perpendicular to each other, areal overlapping in theregion where the front gate and the back gate are facing can bemaximized in the double-gate FET. For this reason, sufficientsuppression of a short channel effect can be expected.

Next, a manufacturing method of the present embodiment will bedescribed.

FIGS. 6A to 6J and FIGS. 7A to 7J describe steps of manufacturing theMRAM according to the first embodiment. FIG. 6A to FIG. 6J are planviews and FIGS. 7A to 7J are cross-sectional views. FIGS. 7A to 7J showcross sections cut in broken lines in FIGS. 6A to 6J, respectively. Inaddition, FIG. 6C, and FIGS. 6E to 6I show states in which a mask hasbeen removed after etching, for simple explanation.

First, as shown in FIG. 6A and FIG. 7A, the active area is patterned ina general manner, similar to the patterning of the layout shown inFIG. 1. More specifically, a mask 11 (SiO₂, SiN, etc.) is deposited onthe silicon substrate 10, and a photoresist pattern is formed on themask 11 by photolithography. Subsequently, the silicon substrate 10 issubjected to selective etching using the processed mask 11, and aninsulation film is filled in a shallow trench formed by the etching toform the device isolation region 12. A region 10 a which is not etchedby the selective etching using the mask 11 but remains becomes theactive area.

Next, to cut the active area at several times and obtain a desiredshape, a mask 13 for a first active area cut is formed as shown in FIG.6B and FIG. 7B. In other words, the mask 13 having an opening 13 a isformed at the first active area portion. After that, the active area ina region which is not covered with the mask 13 and the device isolationregion 12 are etched as shown in FIG. 6C and FIG. 7C. To avoidinconvenience in the formation of an embedded insulation film at formingthe device isolation region later, depths of their etching shoulddesirably correspond to a depth of the first device isolation region 12as much as possible. The portion left by the etching becomes a region 22where the contact is to be formed.

Next, a necessary portion is backfilled with silicon by executingepitaxial growth of silicon 10 b in a region where silicon is exposed,other than the contact pad island region and the device isolationregion, as shown in FIG. 6D and FIG. 7D. The silicon redundantlysubjected to epitaxial growth is smoothed as needed. The regionbackfilled with the silicon is processed later to form the channelregion.

The reason for this is that coexistence of the lithography and etchingis highly difficult in process in relation to the oblique pattern, andthe horizontal and vertical pattern. By separate processing both thepatterns, lowering the degree of difficulty is attempted.

Furthermore, second to fifth active area cuts are sequentially executed,and a desired narrow active area (i.e. fin region) is formed. Of course,close attention needs to be paid to pattern displacement, but the narrowfin region can be processed independently of the contact pad region bysuch processing. The mask for processing the active area has so called ahole type pattern. A desired pattern cannot be wholly formed due tolimitation to the lithography for the hole-type pattern. For thisreason, patterning in the checker flag type and repeating the etchingare currently considered as solution for this problem. In future, if thelithography technology is much more advanced, of course, these hole-typepatterns may be wholly formed at once.

More specifically, a hole-shaped mask 14 for the second active area cutis formed and then the second active area is cut, as shown in FIG. 6Eand FIG. 7E.

After that, a hole-shaped mask 15 for the third active area cut isformed and then the third active area is cut, as shown in FIG. 6F andFIG. 7F.

Next, a hole-shaped mask 16 for the fourth active area cut is formed andthen the fourth active area is cut, as shown in FIG. 6G and FIG. 7G.

After that, a hole-shaped mask 17 for the fifth active area cut isformed and then the fifth active area is cut, as shown in FIG. 6H andFIG. 7H.

The fin-shaped active area 21 is thereby formed.

The basic processing of the active area is thus ended and then the WL(gate electrode) 31 is formed as shown in FIG. 6I and FIG. 7I.

Next, the mask member on the parallelogram contact pad region is removedand the contact region 22 is formed, as shown in FIG. 6J and FIG. 7J.Furthermore, the contact plug 25 and the source line 32 to be connectedto the source-side contact region 22 a are formed.

After this step, the MTJ element 40 to be connected to the drain of thetransistor via the contact plug 26 is formed. Then, the structure shownin FIG. 4 is completed by forming the contact plug 27 and the bit line33 to be connected to the other end of the MTJ element 40.

A cross-sectional view seen when a cell transistor is cut in a direction(horizontal direction) vertical with the WL long side direction is shownin FIG. 5A. The height of the silicon subjected to epitaxial growth ofthe region which is to be the channel is set to be equal to the heightof the contact pad region from which the mask member is to be removed.For this reason, if the mask member is removed from the contact padregion to expose the silicon, the highest portion of the contact padportion silicon becomes lower than the silicon channel portion.Accordingly, in the present embodiment, the fin-FET is shaped to bedifferent in contact height (position) from a general Fin-FET.

In the conventional Fin-FET, the contact region (position of contactbetween the contact plug and the source/drain regions) is the same orhigher than the channel region, since the channel region and thesource/drain regions are equal in height or raised S/D structure byepitaxial growth is adopted. Oppositely, if the contact region is lower,suppression of the short channel effect becomes difficult, since acurrent path flows under the fin. In fact, however, the region lowerthan the gate electrode is somewhat devised to prevent an off-leakagecurrent in the Fin-FET. For example, an impurity concentration is set tobe higher in a region deeper than the gate region. For this reason, evenif the contact region is somewhat lower than the channel region,practical problems rarely arise with respect to off-leakage.

Since an effective channel width becomes great by adopting the Fin-FETlike the present structure as a cell transistor, the channel resistanceitself is reduced. Furthermore, since the current path from the S/D caneasily flow to the lower side of the fin, sufficient suppression of theshort channel effect can contribute to the high current drive.

Thus, according to the present embodiment, the active area 20 forforming the selective transistor for switching is provided along the Xdirection, i.e. in a direction perpendicular to the gate electrode, at aportion (21) crossing the gate electrode. Furthermore, the active area20 is formed to be inclined from the X direction, i.e., shaped in aparallelogram seen from a direction perpendicular to the substratesurface, between adjacent gate electrodes (22). For this reason, thechannel region (21) and the WL region (gate region), of the transistor,can be made perpendicular to each other and the device properties can beimproved. Moreover, since the contact region (22) is formed to be shapedin a parallelogram, the contact region area can be maximized whilemaintaining the distance in device isolation region between contactpads. For this reason, difficulties in various manufacturing processessuch as lithography, etching, and embedment of the insulation film inthe device isolation region can be removed.

In other words, the multi-gate FET represented by the Fin-FET can beformed in the 6F²-type cell layout. Then, the cell transistor capable offorming the current drive force even if downsized, and having littleproperty variation resulting from the channel impurities can be used.The device layout capable of using the cell transistor having aminimized cell area in the memory device, and also having highperformance and suppressed property variation can be therebyimplemented.

(Second Embodiment)

FIG. 8 shows an illustration for describing a concept of an MRAM cellaccording to a second embodiment.

Forming the cell layout in FIG. 1 by the straight lines in the verticaland horizontal directions alone has been considered with reference toFIG. 3, however the manufacturing process is difficult as describedabove. Thus, forming an active area 50 by linear fins alone as shown inFIG. 8 will be considered. To obtain an equivalently similar pattern tothe pattern shown in FIG. 3, however, the fins needs to be partially cutand a contact portion needs to be formed.

In FIG. 8, a circle denoted by 71 presents a region where the finpattern needs to be cut. A source mark region is formed at a markdenoted by 72. It can be understood from this figure that a layoutequivalent to the layout shown in FIG. 4 can be formed if, in FIG. 3,the contact pad region can be removed and two adjacent fins can beconnected by using the contact region similarly to a local interconnect.Thus, the second embodiment aims at implementing the cell layout shownin FIG. 4 based on the pattern formed of an assembly of the fins.

FIG. 9 is a view showing a cell layout of an MRAM according to thesecond embodiment. Like or similar portions to the portions shown inFIG. 4 are denoted by the same reference numbers, and their detailedexplanations are hereinafter omitted.

Fin-shaped active areas 51 for device formation are spaced apart fromeach other at regular intervals, on a silicon substrate (not shown).Each of the active areas 51 is provided along the X direction.

Resistance change elements, for example, MTJ elements 40 arrayed in amatrix in the X direction and the Y direction perpendicular to the Xdirection, are formed over the substrate.

Selective transistors 24 are provided to correspond to the respectiveMTJ elements 40, in the active areas 51. A plurality of gate electrodes31 of the transistors 24 are arranged along the Y direction and spacedapart from each other at regular intervals in an X direction.

Each of the active areas 51 is provided to cross one of the gateelectrodes 31, and the active areas 51 adjacent in the Y direction aredisplaced in the X direction.

A part of side surfaces of the active area 51 is connected to a part ofside surfaces of the other active area 51 via a metal member, to sharesource-side contact regions of the transistors 24 adjacent in the Xdirection. In other words, sources of two transistors 24 adjacent in theX direction are commonly connected with each other at a source-sidecontact portion 41.

Fin-shaped active areas 52 for dummy fins are spaced apart from eachother at regular intervals, on the substrate. The active areas 52 fordummy fins are shorter in the X direction than the active area 51 fordevice formation, and are provided along the X direction withoutcrossing the gate electrodes 31. Furthermore, the active areas 52 fordummy fins are provided in close vicinity of drain portions of theactive area 51 for device formation.

A drain-side contact region of the transistor 24 is formed between apart of the side surface of the active area 51 for device formation andthe side surface of the active area 52 for dummy fins. In other words, apart of the side surface of the active area 51 for device formationforming the drain of the transistor 24 is connected with a part of theside surface of the active area 52 for dummy fins via the metalmaterial.

A source-side contact region and a drain-side contact region of theactive area 51 for device formation are formed on side surfaces oppositeto each other about a center of a long side direction of the active area51 for device formation.

The cell layout further comprises a source line 32 arranged along the Xdirection, and the source-side contact regions of the transistors 24adjacent in the X direction are connected with the same source line 32.

The cell layout further comprises a bit line 33 arranged along the Xdirection, and the MTJ element 40 is connected between the drain-sidecontact region and the bit line 33. In other words, the end of the MTJelement is connected to the drain of the transistor 24 and the other endof the MTJ element is connected to the bit line 33. The MTJ elements 40adjacent in the X direction are connected to different bit lines 33.

Next, a manufacturing method of the present embodiment will be describedwith reference to plan views in FIG. 10A to FIG. 10H and cross-sectionalviews in FIG. 11A to FIG. 11C.

FIG. 10A shows a planar layout formed after processing the fin pattern.This can be formed by repeating the double patterning while noticing amatching accuracy of lithography.

More specifically, fin-shaped active layers 50 having a lengthequivalent to 3F in the X direction are arranged at 4F pitch in the Xdirection and 1F pitch in the Y direction. Furthermore, the activelayers adjacent in the Y direction are displaced by 2F pitch in the Xdirection.

Next, a fin cut mask 61 having circular opening patterns 61 a areprepared to remove an unnecessary fin region, as shown in FIG. 10B.Then, the pattern shown in FIG. 10C is obtained by etching using themask 61. Portions of the fins which are not cut are the active areas 51for device formation and cut portions are the active areas 52 for dummy.

Next, the gate electrodes 31 are formed by depositing gate electrodematerials and processing the materials by lithography and etching, asshown in FIG. 10D. The gate electrodes 31 are arranged along the Ydirection and spaced apart from each other at regular intervals in the Xdirection, similarly to the first embodiment.

Next, contact regions are formed in several steps. This is because metalwiring layers used on the source side and the drain side are different.

First, source-side contact portions 41 are formed as shown in FIG. 10E.At this time, two fins are necessarily connected in the contact regionsuch that a contact falls between the fins, but does not fall to abottom portion of a gap between the fins. FIG. 11A shows a cross sectionof a one-dot-chained line IV-IV′ in FIG. 10E. In FIG. 11A, two fins(active areas for device formation) 51 are connected with each other bya metal 45 embedded in the contact portion 41.

Subsequently, metal wiring of a source line 32 connecting the formedcontact portions 41 is formed. The source lines 32 are arranged alongthe X direction and spaced apart from each other at regular intervals inthe Y direction, similarly to the first embodiment.

Next, drain-side contact portions 43 and 44 are formed to extend betweenthe formed source lines 32, as shown in FIG. 10F and FIG. 10G. FIG. 11Bshows a cross section of a one-dot-chained line V-V′ in FIG. 10G. Theactive areas 51 for device formation and the active areas 52 for dummyare connected by the contact portions 43 and 44 as shown in FIG. 11B.

When the drain-side contact portions 43 and 44 are formed, the formationneeds to be executed in two steps using the double patterning since apattern density of contact is too large to apply single patterningexposure. Furthermore, the drain contact portion 44 formed at the secondtime needs to be displaced slightly vertically from the drain contactportion 43 formed at the first time, in relation to the fins connectedby using the contact portions. This matter needs to be considered mostcarefully when the layout shown in FIG. 1 is formed by the fin patternalone.

Next, the MTJ elements 40 are formed to be connected to the drain-sidecontact portions 43 and 44 as shown in FIG. 10H. At this time, if theMTJ elements 40 are arranged in a grating shape and spaced apart withregular intervals, the arrangement is advantageous in lithography andprocessing. A cross section of a one-dot-chained line VI-VI′ in FIG. 10His shown in FIG. 11C. The MTJ elements 40 are arranged on the respectivecontact portions 43 and 44 as shown in FIG. 11C.

Subsequently, the structure shown in FIG. 9 can be obtained by formingthe bit lines 33 to be connected to the MTJ elements 40 in the Xdirection. The bit lines 33 are formed above the source lines 32 and canbe connected to the other ends of the MTJ elements 40.

Two active areas AA1 and AA2 of the plural of the active areas 51 fordevice formation, two word lines WL1 and WL2 of the plural of word lines31, and a bit line BL1 of the plural of bit lines 33 shown in FIG. 9 arenoticed here.

The active area AA1 is provided to be perpendicular with the word lineWL1, and a first selective transistor is formed in the active area AA1.The active area AA2 is provided to be perpendicular with the word lineWL2, and a second selective transistor is formed in the active area AA2.The active areas AA1 and AA2 are displaced from each other in the Ydirection.

The contact portion 41 to connect sources of first and second selectivetransistors is formed by connection of side surface portions of therespective active areas AA1 and AA2, between the word lines WL1 and WL2.A first resistance change element MTJ1 is connected between the bit lineBL1 and a drain of the first selective transistor. A second resistancechange element MTJ2 is connected between the bit line BL1 and a drain ofthe second selective transistor.

In other words, a first cell is formed of the active area AA1, the wordline WL1, the first resistance change element MTJ1, and the bit lineBL1, and a second cell is formed of the active area AA2, the word lineWL2, the second resistance change element MTJ2, and the bit line BL1.Then, a number of cells can be arranged by spacing the first and secondcells that are considered as basic structures at regular intervals.

Thus, in the present embodiment, the contact regions can be formedwithout contact pad regions when a multi-gate FET represented by aFin-FET is used in the resistance change type memory cell. In otherwords, the Fin-FET can be used as the cell transistor without thecontact pad regions. In addition, the current path can be connected tothe source line and the bit line, by defining formation of the sourcesand the drain contact regions of the Fin-FET at symmetrical positionsabout the fins and by obliquely extending the current path. In otherwords, the current path can be formed in the same direction as theoblique active area shown in FIG. 1. Advantages similar to theadvantages of the first embodiment can be therefore obtained.

In addition, the source-side contact is formed at the center of the finswhere the channel is formed, and can be supplied with a current uniformfor both the fins. In other words, the contact pad-less Fin-FET can beused as a cell transistor. Furthermore, the embodiment also has anadvantage that the drain-side contacts arranged more closely to eachother can be subjected to lithography and processing and that thedrain-side contacts can be connected to the bit lines.

(Modified Embodiment)

The invention is not limited to the above-described embodiments.

The invention is characterized by the cell layout, and the material ofeach portion is not limited at all. The resistance change element is notlimited to the MTJ element, but may be any element that has a resistancevalue changing in accordance with the storing status.

In addition, the method of forming the active area is not limited to theembodiments, and can be modified arbitrarily. For example, iflithography can be much improved and executed, the pattern of the firstembodiment shown in FIG. 10 can be formed by executing etching at onetime. Furthermore, by further improving the accuracy of lithography, thesteps of the second embodiment shown in FIG. 6A to FIG. 6G can beomitted and the pattern shown in FIG. 6H can be formed directly.

In addition, in the second embodiment, if sufficient contact with theMTJ elements can be formed without the active areas for dummy, theactive layer for dummy can be omitted.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A magnetoresistive memory device, comprising:active areas arranged and spaced apart at first intervals, on asemiconductor substrate, each of the active areas being provided alongan X direction; resistance change elements arrayed in a matrix, in an Xdirection and a Y direction perpendicular to the X direction, above thesubstrate; and selective transistors provided to correspond to theresistance change elements, in the active areas, wherein: gateelectrodes of the selective transistors are spaced apart at secondintervals in the X direction and arranged along the Y direction, each ofthe active areas is provided to cross one of the gate electrodes, andeach of the active areas includes a source region, a drain region, and achannel region of one of the selective transistors, in two of the activeareas adjacent to each other and crossing different gate electrodes, apart of side surfaces of one of the active areas is connected to a partof side surfaces of the other of the active areas to share the sourceregion of one of the selective transistors.
 2. The device of claim 1,wherein each of the selective transistors is a Fin-FET.
 3. The device ofclaim 1, further comprising active areas for a dummy pattern arrangedand spaced apart at third intervals, on the substrate, wherein theactive areas for the dummy pattern are shorter than the active areas, inthe X direction, provided along the X direction without crossing thegate electrodes, and provided in close vicinity of drain portions of theselective transistors in the active areas.
 4. The device of claim 3,wherein a part of a side surface of the active areas is connected to aside surface of each of the active areas for dummy pattern via a metalmaterial so as to form the drain region at each of the selectivetransistors.
 5. The device of claim 4, wherein in each of the activeareas, the source region and the drain region are formed on sidesurfaces mutually opposite to each other relative to an axis of symmetryperpendicular to a longer side direction of the active area.
 6. Thedevice of claim 4, wherein an angle θ formed between a direction linkinga central portion of the source region and a central portion of thedrain region, and the X direction, is an angle presented as θ=tan⁻¹(⅓).7. The device of claim 4, further comprising: a source line arrangedalong the X direction; and a bit line arranged along the X direction,wherein the source region of one of the select transistors is connectedto the source line, and each of the resistance change elements isconnected between the drain region and the bit line.
 8. The device ofclaim 7, wherein the resistance change elements adjacent in the Xdirection are connected to different bit lines.
 9. The device of claim1, wherein: longer side directions of the active areas are set to beperpendicular to the Y direction, and connection of the two active areasare made via a metal material.
 10. A magnetoresistive memory device,comprising: first and second word lines arranged parallel to each other;a first active area, for formation of a first selective transistor, alonger side of the first active area being perpendicular to the firstword line, the first active area including a source region, a drainregion, and a channel region of the first selective transistor; a secondactive area, for formation of a second selective transistor, a longerside of the second active area being perpendicular to the second wordline, the second active area including a source region, a drain region,and a channel region of the second selective transistor; a contactmodule which contacts the source regions of the first and secondselective transistors by connection of side surface portions of therespective first and second active areas, between the first and secondword lines; a first resistance change element connected between a bitline perpendicular to the first and second word lines, and a drain ofthe first selective transistor; and a second resistance change elementconnected between the bit line and a drain of the second selectivetransistor.
 11. The device of claim 10, wherein each of the first andsecond selective transistors is a Fin-FET.